Analog-to-digital converters (ADCs) are utilized in a wide variety of electronic devices and systems to transform an analog signal to a digital signal. One ADC architecture commonly used due to its simple implementation is the single-ramp ADC. Conventional single-ramp ADCs, however, are limited to the number of resolution bits they are able to produce due to having an exponentially increasing counter frequency for each additional bit of resolution.
Another commonly used architecture is the two-stage ramp ADC, which extracts the signal residue of a coarse conversion stage and uses that signal residue to perform the fine conversion. The two-stage ramp ADC, however, also suffers from problems due to the settling time of the coarse conversion stage. In particular, the conversion rate of the two-stage ramp ADCs is limited due to the settling time associated with the staircase waveform of the coarse stage, especially when a large number of ADCs are connected to a common staircase waveform signal, such as in CMOS (complementary metal-oxide semiconductor) image sensing integrated circuits.